One of the possible debugging tools used by programmers and software engineers is the hardware instruction breakpoint capability found in many digital processors. As would be understood by a person skilled in the art, an instruction breakpoint occurs when an instruction which is about to be executed has been marked as a breakpointed instruction. Typically, the primary function of hardware instruction breakpoints in processors of the prior art is to permit a debugger (using other external hardware resources) to cause instruction execution to stop when a particular instruction is executed.
Traditional approaches to providing hardware breakpoints do not work correctly, however, when the processor incorporates a prefetch queue. When a microprocessor has a prefetch queue, the instruction addresses to be fetched which appear at the external interface of the chip or even at the external interface of the processor core are not necessarily executed. Even though an instruction is fetched, a preceding instruction in the queue may cause a transfer of execution before later instructions in the queue are executed. The problem then becomes one of matching against addresses as they are decoded for execution. These addresses, however, are generally not observable outside of the processor core. In addition, it is sometimes useful to have an instruction address match cause a trigger to a counter or some monitoring hardware, rather than only interrupt processor execution. This triggering capability is not found in prior art systems. The breakpoint problem is further compounded if multiple hardware breakpoints are provided. In this case, instructions which are breakpointed must be associated with a particular breakpoint.
One prior art attempt at addressing the problem of providing instruction breakpoints in a processor having a prefetch queue can be found in some Motorola background debug mode-equipped processors which includes a break pin. By including the break pin, these processors are capable of correctly handling some of the problems presented by the prefetch queue. However, these processors require external matching hardware and cannot handle multiple breakpoints or breakpoints of the trigger variety. Other attempts in the prior art at solving the above problem include processors which jam a break opcode into the prefetch queue. This methodology requires a wide multiplexer in the instruction fetch path, however, which is also undesirable.
Accordingly, there is a need for a more flexible mechanism to implement on-chip hardware instruction breakpoints which handles either break or trigger behavior on multiple breakpoints.